The present invention relates to a NAND flash memory device and method of manufacturing the same. More particularly, the present invention relates to preventing program disturbance memory cells adjacent to drain select transistors and source select transistors in a NAND flash memory device.
A flash memory is a type of a non-volatile memory in which data can be stored even when power is turned off. The flash memory can be electrically programmed and erased and does not need a refresh function of rewriting data at regular intervals. The term “program” refers to the operation of programming data into the memory cells and the term “erase” refers to the operation of erasing data from the memory cells.
The flash memory device can be mainly classified into a NOR flash memory device and a NAND flash memory device depending on the structure of the cell and operation conditions. In the NOR flash memory device, the source of each memory cell transistor is connected to the ground terminal (VSS) to enable program and erase functions for a predetermined address. Accordingly, the NOR flash memory has been mainly used for application fields requiring the high-speed operation.
On the other hand, in the NAND flash memory, a plurality of memory cells are connected in series to form one string. One string is connected to the source and drain. The NAND flash memory has been mainly used for high integration data retention related fields.
FIG. 1 is a circuit wiring diagram of a conventional NAND flash memory device.
Referring to FIG. 1, there are 32 memory cells MC0 to MC31 connected in series between a drain select transistor DST and a source select transistor SST. It should be appreciated that 16 or 64 memory cells could be connected in series, taking device and density into consideration.
In FIG. 1, 32 memory cells form one string and N strings 1-1 to 1-n are disposed. A memory cell (for example, MC0) is controlled by one word line WL0 and forms one page, i.e., the group of memory cells. In FIG. 1, 32 pages are shown.
In the program operation of the NAND flash memory device constructed as shown in FIG. 1, in a non-selected string (for example, 1-1), when a memory cell to be programmed is MC2, the channel voltage of the memory cells MC0, MC1, and MC3-MC31 which will not be programmed is boosted to approximately 8V in order to prevent program disturbance. If the channel voltage rises to about 8V as described above, program disturbance is generated in the memory cells MC0 and MC31 adjacent to the source select transistor SST and the drain select transistor DST.
During the program operation, the gate of an adjacent source select transistor SST is applied with a voltage of 0V, the gate of the drain select transistor DST is applied with a voltage of VCC, and the gates of the memory cells MC0, MC1, and MC3-MC31, which will not be programmed, are applied with a program-prohibit voltage (Vpass) voltage of approximately 10V. Accordingly, the channel voltage of the source select transistor SST is boosted to approximately 0V, the channel voltage of the drain select transistor DST is boosted to approximately 1V and the channel voltage of the memory cells MC0, MC1, MC3-MC31 is boosted to approximately 8V.
In this case, a strong traverse electric field is formed between the source select transistor SST and the memory cell MC0 due to a voltage difference between the channel voltage of 0V of the source select transistor SST and the channel voltage of 8V of the memory cell MC0. A strong traverse electric field is also formed between the drain select transistor DST and the memory cell MC31 due to a voltage difference between the channel voltage of 1V of the drain select transistor DST and the channel voltage of 8V of the memory cell MC31.
If a strong electric field is generated in a traverse direction as described above, electrons, which are generated at the interface between the gate oxide film of the source select transistor SST and the silicon substrate, become hot electrons while moving toward the memory cell MC0 along the surface of the silicon substrate. The hot electrons generated as described above move in a longitudinal direction and are then introduced into the floating gate of the memory cell MC0 that should not be programmed, thereby programming data into the memory cell MC0 within a non-selected string 1-1. The drain select transistor DST has a gate voltage, which is relatively higher than that of the source select transistor SST. Accordingly, the number of electrons in the drain select transistor DST is relatively smaller than that in the source select transistor SST. As a result, program disturbance is lower in memory cell MC31 than in memory cell MC0.
FIG. 2 is a graph illustrating the relationship between a threshold voltage (Vt) and a program-prohibit voltage (Vpass) of the memory cells MC0, MC31 (i.e., memory cells in which program disturbance has occurred because of hot electrons).
From FIG. 2, it can be seen that the memory cells MC0, M31 connected to the first and last word lines WL0, WL31 have different characteristics from those of the memory cells MC1 to MC30 connected to the remaining word lines WL1 to WL30. This is because program disturbance has occurred due to hot electrons as described above.
The program disturbance phenomenon shown in FIG. 2 becomes severe as the size of the memory cell becomes small and also becomes severe in multi-level cells. The program disturbance phenomenon is undesirable in that it degrades the performance of devices.